1. Field of the Invention
The present invention relates to memory devices, in particular, semiconductor memory devices, and most particularly, scalable, power-efficient semiconductor memory devices.
2. Background of the Art
Memory structures have become integral parts of modern VLSI systems, including digital signal processing systems. Although it typically is desirable to incorporate as many memory cells as possible into a given area, memory cell density is usually constrained by other design factors such as layout efficiency, performance, power requirements, and noise sensitivity.
In view of the trends toward compact, high-performance, high-bandwidth integrated computer networks, portable computing, and mobile communications, the aforementioned constraints can impose severe limitations upon memory structure designs, which traditional memory system and subcomponent implementations may fail to obviate.
One type of basic storage element is the static random access memory (SRAM), which can retain its memory state without the need for refreshing as long as power is applied to the cell. In an SRAM device, the memory state II usually stored as a voltage differential within a bistable functional element, such as an inverter loop. A SRAM cell is more complex than a counterpart dynamic RAM (DRAM) cell, requiring a greater number of constituent elements, preferably transistors. Accordingly, SRAM devices commonly consume more power and dissipate more heat than a DRAM of comparable memory density, thus efficient; lower-power SRAM device designs are particularly suitable for VLSI systems having need for high-density SRAM components, providing those memory components observe the often strict overall design constraints of the particular VLSI system. Furthermore, the SRAM subsystems of many VLSI systems frequently are integrated relative to particular design implementations, with specific adaptions of the SRAM subsystem limiting, or even precluding, the scalability of the SRAM subsystem design. As a result SRAM memory subsystem designs, even those considered to be xe2x80x9cscalablexe2x80x9d, often fail to meet design limitations once these memory subsystem designs are scaled-up for use in a VLSI system with need for a greater memory cell population and/or density.
There is a need for an efficient, scalable, high-performance, low-power memory structure that allows a system designer to create a SRAM memory subsystem that satisfies strict constraints for device area, power, performance, noise sensitivity, and the like.
The invention is useful in a memory component including a dummy cell with a dummy bit line and a plurality of wordlines, the memory component having a memory component capacitance and memory component operational characteristics, including dummy bitline capacitance of the dummy bitline. In such an environment, a diffusion replica delay circuit can be implemented by a method comprising:
a. coupling a diffusion replica capacitor to the dummy bit line and one wordline of the plurality of wordlines, coupling the diffusion replica capacitor to the memory component, storing in the diffusion replica capacitor a predetermined replica charge representative of the dummy bitline capacitance, and matching the diffusion replica capacitance of the diffusion replica capacitor to the dummy bitline capacitance, and
b. coupling a diffusion replica transistor with the diffusion replica capacitor, and coupling the diffusion replica transistor between the diffusion replica capacitor and a charge sink, the transistor being disposed to control the magnitude of the predetermined replica charge.
The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the following drawings.